- CPU : Intel 8048 @ 11Mhz (733.333 Kips performance)
733 Kips <= 11Mhz divided by 15
- Sound : National Semiconductor COP411L @ 52.632 kHz
Clock is generated by unaccurate RC circuit (~13% error)
- RAM: 64 bytes (8048 internal), 1KB (on main PCB)
- ROM: 1KB (BIOS, 8048 internal), 4KB (Cartridge)
- Input: 4 direction joystick, 4 buttons duplicated on each side of the joystick
- Graphics: 150×40 monochrome pixels
|Port 1 =>||P1 = 0||P1 = 1|
|$400-$FFF||Cartridge $400-$FFF||Cartridge $400-$FFF|
XRAM (External RAM)
|$000-$0FF||General Storage, 256 Bytes|
|$100-$1FF||Video Bank 1 (Column #1-#50)|
|$200-$2FF||Video Bank 2 (Column #51-#100)|
|$300-$3FF||Video Bank 3 (Column #101-#150)|
I/O Port 1
Bit 0-1 : RAM bank switch
These pins select one of the four 256 banks that external RAM should use.
Bit 2 : BIOS disable
These pin is used to disable or enable the internal BIOS.
When set to 0 the internal BIOS ROM is enabled from $000-$3FF.
When set to 1 the beginning of the cartridge ROM appears at $000-$3FF.
Bit 3-7 : Controller
These pins receive the controller status, inputs are active low.
Note: For inputs to work, the pins need to be outputted with logic 1.
Stick can’t do diagonals.
|Button 1||1||1||0||0||1||Down + Up|
|Button 2||1||0||1||0||1||Down + Right|
|Button 4||0||1||1||0||1||Down + Left|
I/O Port 2
These pins are wired into the address A8 to A11 for cartridge access.
When this pin is set to a logic 1, the LED storage registers are latched into the LED output drivers for a synchronous display change. This pin must be set to 0 before writing to the LED storage registers.
A read from external RAM causes the following:
|0||0||1||LED #1-#8 storage register write|
|0||1||0||LED #9-#16 storage register write|
|0||1||1||LED #17-#24 storage register write|
|1||0||0||LED #25-#32 storage register write|
|1||0||1||LED #33-#40 storage register write|
|1||1||0||COP411 reset register write|
Pins 4-7 are also connected to the COP411 inputs and are used to transfer two sound command nibbles over these lines when the COP411 reset is released. A read from external RAM with P2 at $C0 and data bit D0 set to ’1′ will release the soundchip from reset.
For more in depth information refer to Sound.
Pin 5 to 7 select the LED rows group to be written on external RAM access.
When pin 4 is set to high, all the LED registers are latched all at once into the LED bar.
For more in depth information refer to Graphics.